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march 2009 rev 1 1/70 1 STA335BWSQS 2.1-channel, high-efficiency digital audio system with qsound qhd ? features ! wide supply voltage range ? 4.5 v to 21.5 v operation ? 23-v absolute maximum rating ! 3 power output configurations ? 2 channels of ternary pwm (stereo mode) (2 x 20 w into 8 ? at 18 v) ? 3 channels - left, right using binary and lfe using ternary pwm (2.1 mode) (2 x 9 w + 1x20w into 2x4 ? , 1 x 8 ? at 18 v) ? 2 channels of ternary pwm (2 x 20 w) + stereo line out ternary ! 2.1 channels of 24-bit ddx ? ! 100-db snr and dynamic range ! selectable 32 khz to 192 khz input sample rates ! i 2 c control with selectable device address ! digital gain/attenuation +48 db to -80 db in 0.5-db steps ! soft volume update ! individual channel and master gain/attenuation ! dual independent limiters/compressors ! dynamic range compression or anti-clipping modes ! automodes ? 15 preset crossover filters ? 5 preset anti-clipping modes ? preset night-time listening mode ! individual channel and master soft and hard mute ! independent channel volume and dsp bypass ! automatic zero-detect mute ! automatic invalid input detect mute ! 2-channel i 2 s input data interface ! input and output channel mapping ! 4 x 28-bit user programmable biquads (eq) per channel ! up to 3 different eq coefficients settings can be stored and selected using i 2 c interface ! dc blocking selectable high-pass filter ! selectable de-emphasis ! sub channel mix into left and right channels ! advanced am interference frequency switching and noise-suppression modes ! selectable high or low bandwidth noise-shaping topologies ! variable max power correction for lower full-power thd ! thermal overload and short-circuit protection ! video application supports 576 * f s input mode ! qsound qhd ? ? field proven stereo soundfield enhancement technology ? provides improved audio image width, separation and depth for stereo signals ? synthesizes a 3-d stereo soundfield ! powersso-36 slug down package. powersso-36 slug down table 1. device summary order code package packaging STA335BWSQS powersso-36 slug down tube STA335BWSQS13tr powersso-36 slug down tape and reel www.st.com
contents STA335BWSQS 2/70 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 qsound qhd ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.1 functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5i 2 c bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.1 data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.2 multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.1 current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.2 current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STA335BWSQS contents 3/70 5.4.3 random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.4 random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.5 write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4.6 read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 configuration register a (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.1 master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.2 interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.3 thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.4 thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.5 fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 configuration register b (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.1 serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.2 serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2.3 serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2.4 delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.5 channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3 configuration register c (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3.1 ddx ? power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3.2 ddx ? compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3.3 over-current warning detect adjustment bypass . . . . . . . . . . . . . . . . . . 31 6.4 configuration register d (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.1 high-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.2 de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.3 dsp bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.4 post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.5 biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4.6 dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 33 6.4.7 zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4.8 miamimode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5 configuration register e (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5.1 max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5.2 max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5.3 noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5.4 am mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5.5 pwm speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
contents STA335BWSQS 4/70 6.5.6 distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5.7 zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5.8 soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.6 configuration register f (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.6.1 output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.6.2 invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.6.3 binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 41 6.6.4 lrck double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.6.5 auto eapd on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.6.6 ic power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.6.7 external amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.7 volume control registers (addr 0x06 to 0x0a) . . . . . . . . . . . . . . . . . . . . . 42 6.7.1 mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.7.2 master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.7.3 channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.7.4 channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.7.5 channel 3 and line-output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.8 automode registers (addr 0x0b and 0x0c) . . . . . . . . . . . . . . . . . . . . . . . 44 6.8.1 automode register 1 (address 0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.8.2 automode register 2 (address 0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.8.3 am interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.8.4 bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.9 channel configuration registers (addr 0x0e to 0x10) . . . . . . . . . . . . . . . . 46 6.9.1 tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.9.2 eq bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.9.3 volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.9.4 binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.9.5 limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.9.6 output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.10 tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.10.1 tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.11 dynamics control registers (addr 0x12 to 0x15) . . . . . . . . . . . . . . . . . . . . 48 6.11.1 limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.11.2 limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.11.3 limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.11.4 limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STA335BWSQS contents 5/70 6.12 user-defined coefficient control registers (addr 0x16 to 0x26) . . . . . . . . . 52 6.12.1 coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.2 coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.3 coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.4 coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.5 coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.6 coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.7 coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.8 coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.9 coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.10 coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.12.11 coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.12.12 coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.12.13 coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.12.14 coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.12.15 coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.12.16 coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.12.17 coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.12.18 user-defined eq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.19 pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.20 post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.21 over-current post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.13 variable max power correction registers (addr 0x27 to 0x28) . . . . . . . . . 59 6.14 variable distortion compensation registers (addr 0x29 to 0x2a) . . . . . . . 59 6.15 fault detect recovery constant registers (addr 0x2b to 0x2c) . . . . . . . . . 60 6.16 device status register (addr 0x2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.17 eq coefficients and drc configuration register (addr 0x31) . . . . . . . . . . 61 7 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1 applications schematic and power supplies . . . . . . . . . . . . . . . . . . . . . . . 62 7.2 pll filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.3 typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
contents STA335BWSQS 6/70 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10 license information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11 trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 68 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
STA335BWSQS list of tables 7/70 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. mcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. ir bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. twrb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. twab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. fdrb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16. sai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. saifb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. support serial audio input formats for msb-first (saifb = 0) . . . . . . . . . . . . . . . . . . . . . . . 28 table 19. supported serial audio input formats for lsb-first (saifb = 1) . . . . . . . . . . . . . . . . . . . . . 29 table 20. dscke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 21. cnim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 22. om . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23. output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. csz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 25. compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 26. ocrb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. hpb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 28. demp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 29. dspb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 30. psl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 31. bql. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 32. drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 33. zde. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 34. mme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 35. mpcv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 36. mpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 37. nsbw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 38. ame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 39. pwms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 40. dccv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 41. zce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 42. sve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 43. ocfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 44. output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 45. ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 46. bcle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 47. ldte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 48. ecle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
list of tables STA335BWSQS 8/70 table 49. pwdn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 50. eapd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 51. loc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 52. master volume offset as a function of mv[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 53. channel volume as a function of cxv[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 54. automode gain compression/limiters selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 55. amame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 56. automode am switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 57. xo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 58. bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 59. channel limiter mapping as a function of cxls bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 60. channel output mapping as a function of cxom bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 61. tone control boost/cut as a function of btc and ttc bits . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 62. limiter attack rate as a function of lxa bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 63. limiter release rate as a function of lxr bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 table 64. limiter attack threshold as a function of lxat bits (ac-mode). . . . . . . . . . . . . . . . . . . . . . 51 table 65. limiter release threshold as a function of lxrt bits (ac-mode) . . . . . . . . . . . . . . . . . . . . 51 table 66. limiter attack threshold as a function of lxat bits (drc-mode) . . . . . . . . . . . . . . . . . . . . 52 table 67. limiter release threshold as a as a function of lxrt bits (drc-mode) . . . . . . . . . . . . . . . 52 table 68. ram block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 58 table 69. sel bitfield description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 70. amgc bitfield description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 71. amgc bitfield description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 72. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 73. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
STA335BWSQS list of figures 9/70 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. pins of powersso-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4. test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. STA335BWSQS processing data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. ocfg = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 10. ocfg = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. ocfg = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. STA335BWSQS output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. 2.0 channels (ocfg = 00) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 14. 2.1 channels (ocfg = 01) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15. 2.1 channels (ocfg = 10) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16. basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 18. pll application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 19. output configuration for stereo btl mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 20. double-layer pcb with copper ground area and 16 via holes . . . . . . . . . . . . . . . . . . . . . . 64 figure 21. powersso-36 power derating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 22. powersso-36 (slug-up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 66
description STA335BWSQS 10/70 1 description 1.1 description the STA335BWSQS is an integration of digital audio processing, digital amplifier control, ddx ? power-output stage and qsound qhd ? technology to create a high-power single-chip ddx solution comprising high-quality, high-efficiency and all digital amplification. the STA335BWSQS is part of the soundterminal? family that provides full digital audio streaming to the speaker offering cost effectiveness, low power dissipation and sound enrichment. the STA335BWSQS power section consists of four independent half-bridges. these can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge, providing up to 2 x 9 w + 1 x 20 w of power output. two channels can be provided by two full-bridges, providing up to 2 x 20 w of power. the ic can also be configured as a 2.1 channels with 2 x 20 w provided by the device and external power for ddx ? power drive. also provided in the STA335BWSQS are a full assortment of digital processing features. this includes up to four programmable 28-bit biquads (eq) per channel, and bass/treble tone control. automodes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. this includes auto volume loudness, preset volume curves and preset eq settings. new advanced am radio-interference reduction modes. the serial audio data input interface accepts all possible formats, including the popular i 2 s format. three channels of ddx ? processing are provided. this high-quality conversion from pcm audio to ddx-patented 3-state pwm switching waveform provides over 100 db of snr and dynamic range. 1.2 qsound qhd ? normally, reduced audio clarity is experienced due to the digital compression of music (and video-sound) combined with various audio processing techniques used in broadcast transmission. this is most apparent in prod ucts such as digital televisions and audio players. these devices are faced with a multitude of audio challenges, primarily associated with the small speakers, that are limited in location and cabinet housing, plus economized speaker drivers and components. as such, digital televisions and audio players are ideal candidates to benefit from stereo soundfield enhancement in order to deliver a full surround-like experience. qsound qhd ? and its industry recognized qxpander ? technology is a field-proven stereo soundfield enhancement technology that provides a broader stereo image width with greater separation and depth for stereo signals and synthesizes a 3-d stereo soundfield. qhd ? removes the small centralized audio sweet spot by creating a very wide stereo image with full immersive audio. qhd ? and its qxpander ? technology have been incorporated into hundreds of qsound and third party hardware and software products, with total shipments in the millions.
STA335BWSQS description 11/70 1.3 block diagram figure 1. block diagram protection current/thermal logic regulators bias power control ddx pll volume control channel 1a channel 1b channel 2a channel 2b i 2 s interface power digital (dsp) i 2 c
pin list STA335BWSQS 12/70 2 pin list 2.1 pinout diagram figure 2. pins of powersso-36 (top view) 2.2 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vdd_dig gnd_dig scl sda int_line reset sdi lrcki bicki xti pll_gnd filter_pll vdd_pll pwrdn gnd_dig vdd_dig twarn/out4b eapd/out4a gnd_sub sa test_mode vss vcc_reg out2b gnd2 vcc2 out2a out1b vcc1 gnd1 out1a gnd_reg vdd config out3b/ddx3b out3a/ddx3a d05au1638 table 2. pin description pin type name description 1 gnd gnd_sub substrate ground 2i sai 2 c select address 3 i test_mode this pin must be connected to ground 4 i/o vss internal reference at vcc - 3.3 v 5 i/o vcc_reg internal vcc reference 6 o out2b output half bridge 2b 7 gnd gnd2 power negative supply 8 power vcc2 power positive supply
STA335BWSQS pin list 13/70 9 o out2a output half bridge 2a 10 o out1b output half bridge 1b 11 power vcc1 power positive supply 12 gnd gnd1 power negative supply 13 i/o out1a output half bridge 1a 14 gnd gnd_reg internal ground reference 15 power vdd internal 3.3 v reference voltage 16 i config paralleled mode command 17 o out3b/ddx3b pwm out ch3b - external bridge 18 o out3a/ddx3a pwm out ch3a - external bridge 19 o eapd/out4a power down for external bridge 20 i twarn/out4b thermal warning from external bridge 21 power vdd_dig digital supply voltage 22 gnd gnd_dig digital ground 23 i pwrdn power down 24 power vdd_pll positive supply for pll 25 i filter_pll connection to pll filter 26 gnd gnd_pll negative supply for pll 27 i xti pll input clock 28 i bicki i 2 s serial clock 29 i lrcki i 2 s left/right clock 30 i sdi i 2 s serial data channels 1 and 2 31 i reset reset 32 o int_line fault interrupt 33 i/o sda i 2 c serial data 34 i scl i 2 c serial clock 35 gnd gnd_dig digital ground 36 power vdd_dig digital supply voltage table 2. pin description (continued) pin type name description
electrical specifications STA335BWSQS 14/70 3 electrical specifications 3.1 absolute maximum ratings note: stresses beyond those listed under ?absolute maximum ratings? make cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating condition? are not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. in the re al application, power supply with nominal value rated inside recommended operating conditions, may experience some rising beyond the maximum operating condition for short time when no or very low current is sinked (amplifier in mute state). in this case the reliability of the device is guaranteed, pr ovided that the absolute maximum rating is not exceeded. 3.2 recommended operating condition table 3. absolute maximum ratings symbol parameter min typ max unit v cc power supply voltage (vcc1, vcc2) -0.3 23 v vdd_dig digital supply voltage -0.3 4 v vdd_pll pll supply voltage -0.3 4 t op operating junction temperature 0 150 c t stg storage temperature -40 150 c table 4. recommended operating condition symbol parameter min typ max unit v cc power supply voltage (vcc1, vcc2) 4.5 21.5 v vdd_dig digital supply voltage 2.7 3.3 3.6 v vdd_pll pll supply voltage 2.7 3.3 3.6 v t amb ambient temperature -20 70 c
STA335BWSQS electrical specifications 15/70 3.3 electrical specificat ions - digital section 3.4 electrical specific ations - power section the specifications given in this sect ion are with the operating conditions v cc = 18 v, f=1khz, f sw = 384 khz, t amb = 25 c, r l = 8 ? , unless otherwise specified. table 5. electrical specifications - digital section symbol parameter cond itions min typ max unit i il low level input current without pull device vi = 0 v -10 10 a i ih high level input current without pull device vi = vdd_dig = 3.6 v -10 10 a v il low level input voltage 0.2 * vdd_dig v v ih high level input voltage 0.8 * vdd_dig v v ol low level output voltage i ol = 2 ma 0.4 * vdd_dig v v oh high level output voltage i oh = 2 ma 0.8 * vdd_dig v i pu pull current -25 66 125 a r pu equivalent pull resistance 50 k ? table 6. electrical specifications - power section symbol parameter conditions min typ max unit po output power btl v cc = 18 v thd = 1% 16 w thd = 10% 20 output power se v cc = 18v thd = 1% 4 w thd = 10% 5 r dson power pchannel/nchannel mosfet (total bridge) l d = 1.5 a 180 250 m ? gp power pchannel rdson matching l d = 1.5 a 95 % gn power nchannel rdson matching l d = 1.5 a 95 % i dss power pchannel/nchannel leakage ldss v cc = 20 v 10 a g p power pchannel rdson matching l d = 1.5 a 95 % g n power nchannel rdson matching l d = 1.5 a 95 % idss power pchannel/nchannel leakage v cc = 20 v 10 a i ldt low current dead time (static) resistive load (1) 8 15 ns i hdt high current dead time (dynamic) i load = 1.5 a (1) 15 30 ns
electrical specifications STA335BWSQS 16/70 t r rise time resistive load (1) 10 18 ns t f fall time resistive load (1) 10 18 ns v cc supply voltage operating voltage 4.5 21.5 v i vcc supply current from vcc in power down pwrdn = 0 0.1 1 ma supply current from vcc in operation pcm input signal = -60 dbfs switching frequency = 384 khz no lc filters 52 60 ma i vdd supply current ddx processing (reference only) internal clock = 49.152 mhz 55 70 ma i lim overcurrent limit (2) 2.2 3.0 4.0 a isc short circuit protec tion hi-z output 2.7 3.6 a uvl under voltage protection 3.5 4.3 v t min output minimum pulse width no load 20 30 60 ns dr dynamic range 100 db snr signal to noise ratio, ternary mode a-weighted 100 db signal to noise ratio binary mode 90 db pssr power supply rejection ratio ddx stereo mode, <5 khz v ripple = 1 v rms audio input = dither only 80 db thd+n total harmonic distortion + noise ddx stereo mode, po = 1 w f = 1 khz 0.2 % x ta l k crosstalk ddx stereo mode, <5 khz one channel driven @ 1 w other channel measured 80 db peak efficiency, ddx mode po = 2 x 20 w into 8 ? 90 % peak efficiency, binary modes po = 2 x 9 w into 4 ? , 1 x 20 w into 8 ? 87 1. refer to figure 4: test circuit 1 . 2. limit current if the register (ocrb par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. when disabled refer to isc. table 6. electrical specifications - power section (continued) symbol parameter conditions min typ max unit
STA335BWSQS electrical specifications 17/70 3.5 power-on sequence figure 3. power-on sequence where: tr = minimum time between xti master clock stable and reset removal: 1 ms, tc = minimum time between reset removal and i 2 c program, sequence start: 1ms. note: clock stable means: f max - f min < 1 mhz note: no specific vccx and vdd_dig turn ? on sequence is required. 3.6 testing 3.6.1 functional pin status don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care table 7. functional pin status pin name pin # logic value ic status pwrdn 23 0 low absorption pwrdn 23 1 normal operation twarn 20 0 from external power stage is indicated a temperature warning twarn 20 1 normal operation eapd 19 0 low absorption for power stage all internal regulators are switched off eapd 19 1 normal operation
electrical specifications STA335BWSQS 18/70 figure 4. test circuit 1 figure 5. test circuit 2 dtr dtf vcc (3/4)vcc (1/2)vcc (1/4)vcc t outxy low current dead time = max(dtr, dtf) +vcc duty cycle = 50% inxy m58 m57 outxy gnd vdc = vcc/2 v67 r 8 ? + - high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=4 ? q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=1.5a iout=1.5a q4 q1 q3 m64 inb m63 d06au1651 m58 ina m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4a in the direction shown in figure l68 10 l67 10 outa
STA335BWSQS processing data paths 19/70 4 processing data paths here after some pictures that represent the data processing paths inside STA335BWSQS. a first 2-times oversampling fir filter allows a 2x fs audio processing. then a selectable high pass filter removes the dc level. 4 biquads filter allow a full equalization system. a final crossover filter is present. this filter can eventually be used as a fifth biquad stage, see the i 2 c registers settings for this specific usage. a prescaler and a final post scaler allow a full control over the signal dynamic respectively before and after the filtering stages. a mixer function is also available. figure 6. STA335BWSQS processing data flow if c2tcb=0 btc: bass boost/cut ttc: treble boost/cut prescale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de- emphasis bass treble if hpb=0 user-defined filters if demp=0 if dspb=0 and c2eqbp=0 x2 fir over sampling r if c1tcb=0 btc: bass boost/cut ttc: treble boost/cut from i2s input interface prescale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de- emphasis bass treble if hpb=0 user-defined filters if demp=0 if dspb=0 and c1eqbp=0 x2 fir over sampling l sampling frequency=fs sampling frequency=2xfs if c2tcb=0 btc: bass boost/cut ttc: treble boost/cut prescale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de- emphasis bass treble if hpb=0 user-defined filters if demp=0 if dspb=0 and c2eqbp=0 x2 fir over sampling r if c1tcb=0 btc: bass boost/cut ttc: treble boost/cut from i2s input interface prescale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de- emphasis bass treble if hpb=0 user-defined filters if demp=0 if dspb=0 and c1eqbp=0 x2 fir over sampling l sampling frequency=fs sampling frequency=2xfs crossover frequency determined by xo setting user defined if xo=0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 hi-pass xo filter hi-pass xo filter lo-pass xo filter user-defined mix coefficients vol and limiter vol and limiter vol and limiter post scale post scale post scale crossover frequency determined by xo setting user defined if xo=0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 channel ? biquad #5 -------------- hi-pass xo filter user-defined mix coefficients vol and limiter vol and limiter vol and limiter post scale post scale post scale channel ? biquad #5 -------------- hi-pass xo filter channel 3 biquad -------------- low-pass xo filter crossover frequency determined by xo setting user defined if xo=0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 hi-pass xo filter hi-pass xo filter lo-pass xo filter user-defined mix coefficients vol and limiter vol and limiter vol and limiter post scale post scale post scale crossover frequency determined by xo setting user defined if xo=0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 channel ? biquad #5 -------------- hi-pass xo filter user-defined mix coefficients vol and limiter vol and limiter vol and limiter post scale post scale post scale channel ? biquad #5 -------------- hi-pass xo filter channel 3 biquad -------------- low-pass xo filter
i 2 c bus specification STA335BWSQS 20/70 5 i 2 c bus specification the STA335BWSQS supports the i 2 c protocol via the input ports scl and sda_in (master to slave) and the output port sda_out (slave to master). this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. STA335BWSQS is always a slav e device in all of its communications. it supports up to 400 kb/s (fast-mode bit rate). STA335BWSQS i 2 c is a slave only interface. 5.1 communication protocol 5.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 5.1.2 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 5.1.3 stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between STA335BWSQS and the bus master. 5.1.4 data input during the data input the STA335BWSQS samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 5.2 device addressing to start communication between the master and the STA335BWSQS, the master must initiate with a start condition. following this, the master sends onto the sda line 8-bits (msb first) corresponding to the device select address and read or write mode. the seven most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the STA335BWSQS the i 2 c interface has two device addresses depending on the sa port configuration, 0x38 when sa = 0, and 0x3a when sa = 1. the eighth bit (lsb) identifies read or write operation rw, this bit is set to 1 in read mode and 0 for write mode. after a start condition the STA335BWSQS identifies on the bus the device address and if a match is found, it acknowledges the identification on sda bus during the 9th bit time. the byte following the device identification byte is the internal space address.
STA335BWSQS i 2 c bus specification 21/70 5.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the STA335BWSQS acknowledges this and the writes for the byte of internal address. after receiving the internal byte address the STA335BWSQS again responds with an acknowledgement. 5.3.1 byte write in the byte write mode the master sends one data byte, this is acknowledged by the STA335BWSQS. the master then terminates the transfer by generating a stop condition. 5.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition terminates the transfer. 5.4 read operation 5.4.1 current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the STA335BWSQS acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 5.4.2 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are read from sequential addresses within the STA335BWSQS. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. 5.4.3 random ad dress byte read following the start condition the master sends a device select code with the rw bit set to 0. the STA335BWSQS acknowledges this and then the master writes the internal address byte. after receiving, the internal byte address the STA335BWSQS again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the STA335BWSQS acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 5.4.4 random address multi-byte read the multi-byte read modes could start from any internal address. sequential data bytes are read from sequential addresses within the STA335BWSQS. the master acknowledges each data byte read and then generates a stop condition terminating the transfer.
i 2 c bus specification STA335BWSQS 22/70 5.4.5 write mode sequence figure 7. write mode sequence 5.4.6 read mode sequence figure 8. read mode sequence dev-addr ack start rw sub-addr ack data in ack stop byte write dev-addr ack start rw sub-addr ack data in ack stop multibyte write data in ack dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no a ck start rw dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data a ck start rw data a ck no a ck stop data rw= high
STA335BWSQS register description 23/70 6 register description you must not reprogram the register bits marked ?reserved?. it is important that these bits keep their default reset values. table 8. register summary addr name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im dscke saifb sai3 sai2 sai1 sai0 0x02 confc ocrb reserved csz3 csz2 csz1 csz0 om1 om0 0x03 confd mme zde drc bql psl dspb demp hpb 0x04 confe sve zce dccv pwms ame nsbw mpc mpcv 0x05 conff eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 0x06 mute/loc loc1 loc0 reserved c3m c2m c1m mmute 0x07 mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x08 c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x09 c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0a c3vol c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0x0b auto1 reserved amgc1 amgc0 reserved 0x0c auto2 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 0x0d auto3 reserved 0x0e c1cfg c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 0x0f c2cfg c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 0x10 c3cfg c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp reserved 0x11 tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x12 l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x13 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x14 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x15 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0x16 cfaddr reserved cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x17 b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x18 b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x19 b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x1a b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x1b b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x1c b2cf3 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0x1d a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16
register description STA335BWSQS 24/70 0x1e a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x1f a1cf3 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 0x20 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x21 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x22 a2cf3 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0x23 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x24 b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x25 b0cf3 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0x26 cfud reserved ra r1 wa w1 0x27 mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x28 mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x29 dcc1 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 0x2a dcc2 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 0x2b fdrc1 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 0x2c fdrc2 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 0x2d status pllul fault uvfault ovfault ocfault ocwarn tfault twarn 0x2e reserved reserved ro1bact r5bact r4bact r3bact r2bact r1bact 0x2f reserved reserved r01bend r5bend r4bend r3bend r2bend r1bend 0x30 reserved reserved r5bbad r4bbad r3bbad r2bbad r1bbad 0x31 eqcfg xob reserved amgc3 amgc2 reserved sel1 sel0 table 8. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
STA335BWSQS register description 25/70 6.1 configuration register a (addr 0x00) 6.1.1 master clock select the STA335BWSQS supports sample rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz. therefore the internal clock is: " 32.768 mhz for 32 khz " 45.1584 mhz for 44.1 khz, 88.2 khz, and 176.4 khz " 49.152 mhz for 48 khz, 96 khz, and 192 khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (f s ). the relationship between the input clock and the input sample rate is determined by both the mcsx and the ir (input rate) register bits. the mcsx bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011 table 9. mcs bit rw rst name description 0rw 1 mcs0 selects the ratio between the input i 2 s sample frequency and the input clock. 1rw 1 mcs1 2rw 0 mcs2 table 10. input sampling rates input sample rate fs (khz) ir mcs[2:0] 101 100 011 010 001 000 32, 44.1, 48 00 576fs 128 fs 256fs 384fs 512fs 768fs 88.2, 96 01 na 64fs 128f s 192fs 256fs 384fs 176.4, 192 1x na 32fs 64fs 96fs 128fs 192fs
register description STA335BWSQS 26/70 6.1.2 interpolation ratio select the STA335BWSQS has variable interpolation (oversampling) settings such that internal processing and ddx output rates remain consis tent. the first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. the oversampling ratio of this interpolation is determined by the ir bits. 6.1.3 thermal warning recovery bypass if the thermal warning adjustment is enabled (twab = 0), then the thermal warning recovery determines if the -3 db output limit is removed when thermal warning is negative. if twrb = 0 and twab = 0, then when a thermal warning disappears the -3 db output limit is removed and the gain is added back to the system. if twrb = 1 and twab = 0, then when a thermal warning disappears the -3 db output limit remains until twrb is changed to zero or the device is reset. table 11. ir bit rw rst name description 4:3 rw 00 ir[1:0] selects internal interpolation ratio based on input i 2 s sample frequency table 12. ir bit settings as a function of input sample rate input sample rate fs (khz) ir 1st stage interpolation ratio 32 00 2 times oversampling 44.1 00 2 times oversampling 48 00 2 times oversampling 88.2 01 pass-through 96 01 pass-through 176.4 10 2 times downsampling 192 10 2 times downsampling table 13. twrb bit rw rst name description 5rw 1 twrb 0: thermal warning recovery enabled 1: thermal warning recovery disabled
STA335BWSQS register description 27/70 6.1.4 thermal warning adjustment bypass the on-chip STA335BWSQS power output block provides feedback to the digital controller using inputs to the power control block. the twarn input is used to indicate a thermal warning condition. when twarn is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces a -3 db output limit (determined by twocl in the coefficient ram) to the modulation limit in an attempt to eliminate the thermal warning condition. once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless fdrb = 0. 6.1.5 fault detect recovery bypass the on-chip STA335BWSQS power output block provides feedback to the digital controller using inputs to the power control block. the faul t input is used to indicate a fault condition (either over-current or thermal). when fault is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 s as defined by the fault-detect recovery constant register (fdrc registers 0x29, 0x2a), then toggles it back to 1. this sequence is repeated as log as the fault indication exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. 6.2 configuration register b (addr 0x01) 6.2.1 serial audio i nput interface format table 14. twab bit rw rst name description 6rw 1 twab 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled table 15. fdrb bit rw rst name description 7rw 0 fdrb 0: fault detect recovery enabled 1: fault detect recovery disabled d7 d6 d5 d4 d3 d2 d1 d0 c2im c1im dscke saifb sai3 sai2 sai1 sai0 1 0 0 0 0000 table 16. sai bit rw rst name description 0 rw 0 sai0 determines the interface format of the input serial digital audio interface. 1 rw 0 sai1 2 rw 0 sai2 3 rw 0 sai3
register description STA335BWSQS 28/70 6.2.2 serial data interface the STA335BWSQS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA335BWSQS always acts a slave when receiving audio input from standard digital audio components. serial data for two channels is provided using three inputs: left/right clock lrcki, serial clock bicki, and serial data 1 and 2 sdi12. the sai register (configuration register b (0x01), bits d3 to d0) and the saifb register (configuration register b (0x01), bit d4) are used to specify the serial data format. the default serial data format is i 2 s, msb-first. available formats are shown in the tables and figure that follow. 6.2.3 serial data first bit table 17. saifb saifb format 0 msb-first 1 lsb-first table 18. support serial audio input formats for msb-first (saifb = 0) bicki sai [3:0] saifb interface format 32fs 0000 0 i 2 s 15-bit data 0001 0 left/right-justified 16-bit data 48fs 0000 0 i 2 s 16 to 23-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data 64fs 0000 0 i 2 s 16 to 24-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data
STA335BWSQS register description 29/70 6.2.4 delay serial clock enable table 19. supported serial audio input formats for lsb-first (saifb = 1) bicki sai [3:0] saifb interface format 32fs 1100 1 i 2 s 15-bit data 1110 1 left/right-justified 16-bit data 48fs 0100 1 i 2 s 23-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data 64fs 0000 1 i 2 s 24-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data table 20. dscke bit rw rst name description 5rw 0 dscke 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some i2s master devices
register description STA335BWSQS 30/70 6.2.5 channel input mapping each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping re gisters. this allows for flexib ility in processi ng. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. 6.3 configuration register c (addr 0x02) 6.3.1 ddx ? power output mode the ddx power output mode selects how the ddx output timing is configured. different power devices use different output modes. table 21. cnim bit rw rst name description 6rw 0 c1im 0: processing channel 1 receives left i 2 s input 1: processing channel 1 receives right i 2 s input 7rw 1 c2im 0: processing channel 2 receives left i 2 s input 1: processing channel 2 receives right i 2 s input d7 d6 d5 d4 d3 d2 d1 d0 ocrb reserved csz3 csz2 csz1 csz0 om1 om0 1 010111 table 22. om bit rw rst name description 0rw 1 om0 selects configuration of ddx output. 1rw 1 om1 table 23. output modes om[1,0] output stage mode 00 drop compensation 01 discrete output stage - tapered compensation 10 full power mode 11 variable drop compensation (cszx bits)
STA335BWSQS register description 31/70 6.3.2 ddx ? compensating pulse size register table 6: 6.3.3 over-current warning detect adjustment bypass the ocwarn input is used to indicate an over-current warning condition. when ocwarn is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default is -3 db) in an attempt to eliminate the over-current warning condition. once the over-current warning volume adjustment is app lied, it remains in this state until reset is applied. the level of adjustment can be changed via the twocl (thermal warning/over current limit) setting which is address 0x37 of the user defined coefficient ram. table 24. csz bit rw rst name description 2rw 1 csz0 when om[1,0] = 11, this register determines the size of the ddx compensating pulse from 0 clock ticks to 15 clock periods. 3rw 0 csz1 4rw 1 csz2 5rw 0 csz3 table 25. compensating pulse size csz[3:0] compensating pulse size 0000 0 ns (0 tick) compensating pulse size 0001 20 ns (1 tick) clock period compensating pulse size ?? 1111 300 ns (15 ticks) clock period compensating pulse size table 26. ocrb bit rw rst name description 7 rw 1 ocrb 0: over-current warning adjustment enabled 1: over-current warning adjustment disabled
register description STA335BWSQS 32/70 6.4 configuration register d (addr 0x03) 6.4.1 high-pass filter bypass the STA335BWSQS features an internal digital high-pass filter for the purpose of ac coupling. the purpose of this filter is to prevent dc signals from passing through a ddx ? amplifier. dc signals can cause speaker damage. when hpb = 0, this filter is enabled. 6.4.2 de-emphasis setting the demp bit enables de-emphasis on all channels 6.4.3 dsp bypass setting the dspb bit bypasses the eq functionality of the STA335BWSQS. 6.4.4 post-scale link post-scale functionality can be used for power-supply error correction. for multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. d7 d6 d5 d4 d3 d2 d1 d0 mme zde drc bql psl dspb demp hpb 01000000 table 27. hpb bit rw rst name description 0rw 0 hpb setting of one bypasses internal ac coupling digital high-pass filter table 28. demp bit rw rst name description 1rw 0 demp 0: no de-emphasis 1: de-emphasis table 29. dspb bit rw rst name description 2 rw 0 dspb 0: normal operation 1: bypass of biquad and bass/treble functionality table 30. psl bit rw rst name description 3 rw 0 psl 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value
STA335BWSQS register description 33/70 6.4.5 biquad coefficient link for ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. 6.4.6 dynamic range compre ssion/anti-clipping bit both limiters can be used in one of two ways, anti-clipping or dynamic range compression. when used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. in dynamic range compression mode the limiter threshold values vary with the volume settings allowing a night-time listening mode that provides a reduction in the dynamic range regardless of the volume level. 6.4.7 zero-detect mute enable setting the zde bit enables the zero-detect automatic mute. the zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 6.4.8 miamimode enable table 31. bql bit rw rst name description 4rw 0 bql 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values table 32. drc bit rw rst name description 5 rw 0 drc 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode table 33. zde bit rw rst name description 6 rw 1 zde 1: enable the automatic zero-detect mute table 34. mme bit rw rst name description 7rw 0 mme 0: sub mix into left/right disabled 1: sub mix into left/right enabled
register description STA335BWSQS 34/70 6.5 configuration register e (addr 0x04) 6.5.1 max power correction variable 6.5.2 max power correction setting the mpc bit turns on special processing that corrects the STA335BWSQS power device at high power. this mode should lower the thd+n of a full ddx system at maximum power output and slightly below. if enabled, mpc is operational in all output modes except tapered (om[1,0] = 01) and bina ry. when ocfg = 00, mpc will not effect channels 3 and 4, the line-out channels. 6.5.3 noise-shaper bandwidth selection 6.5.4 am mode enable STA335BWSQS features a ddx processing mo de that minimizes the amount of noise generated in frequency range of am radio. this mode is intended for use when ddx is operating in a device with an am tuner active. the snr of the ddx processing is reduced to approximately 83 db in this mode, which is still greater than the snr of am radio. d7 d6 d5 d4 d3 d2 d1 d0 sve zce dccv pwms ame nsbw mpc mpcv 11000010 table 35. mpcv bit rw rst name description 0rw 0 mpcv 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient table 36. mpc bit rw rst name description 1rw 1 mpc 1: enable power bridge correction for thd reduction near maximum power output. table 37. nsbw bit rw rst name description 2 rw 0 nsbw 1: third order ns 0: fourth order ns table 38. ame bit rw rst name description 3rw 0 ame 0: normal ddx operation. 1: am reduction mode ddx operation
STA335BWSQS register description 35/70 6.5.5 pwm speed mode 6.5.6 distortion compe nsation variable enable 6.5.7 zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks are audible. 6.5.8 soft volume update enable table 39. pwms bit rw rst name description 4rw 0 pwms 0: normal speed (384 khz) all channels 1: odd speed (341.3 khz) all channels table 40. dccv bit rw rst name description 5 rw 0 dccv 0: uses preset dc coefficient 1: uses dcc coefficient table 41. zce bit rw rst name description 6rw 1 zce 1: volume adjustments only occur at digital zero-crossings 0: volume adjustments occur immediately table 42. sve bit rw rst name description 7rw 1 sve 1: volume adjustments ramp according to svr settings 0: volume adjustments occur immediately
register description STA335BWSQS 36/70 6.6 configuration register f (addr 0x05) 6.6.1 output configuration note: to the left of the arrow is the processing channel. when using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 01011100 table 43. ocfg bit rw rst name description 0rw 0 ocfg0 selects the output configuration 1rw 0 ocfg1 table 44. output configuration engine selection ocfg[1:0] output configuration config pin 00 2 channel (full-bridge) power, 2 channel data-out: 1a/1b 1a/1b 2a/2b 2a/2b lineout1 3a/3b lineout2 4a/4b line out configuration determined by loc register 0 01 2 (half-bridge), 1 (full-bridge) on-board power: 1a 1a, binary 0 2a 1b, binary 90 3a/3b 2a/2b, binary 45 1a/b 3a/b, binary 0 2a/b 4a/b, binary 90 0 10 2 channel (full-bridge) power, 1 channel ddx: 1a/1b 1a/1b 2a/2b 2a/2b 3a/3b 3a/3b eapdext and twarnext active 0 11 1 channel mono-parallel: 3a 1a/1b, w/ c3bo 45 3b 2a/2b, w/ c3bo 45 1a/1b 3a/3b 2a/2b 4a/4b 1
STA335BWSQS register description 37/70 STA335BWSQS can be configured to support different output configurations. for each pwm output channel a pwm slot is defined. the pwm slot always has a time duration of 1/(8 * fs) seconds. the pwm slot defines the maximum extension for pwm rising and falling edges, that is, rising edg e as far as the falling edge cannot range outsi de pwm slot boundaries. figure 12. STA335BWSQS output mapping scheme figure 9. ocfg = 00 (default value) figure 10. ocfg = 01 figure 11. ocfg = 10 ocfg = 11 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 lpf lineout 1 out3b lpf lineout 2 out4b out4a out3a half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 channel 1 channel 2 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 power device out3b out3a eapd channel 3 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 out3b out4b out4a out3a channel 1 channel 2 ddx? modulator remap ddx1a ddx1b ddx2a ddx2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ddx3a ddx3b ddx4a ddx4b out3a out3b out4a out4b
register description STA335BWSQS 38/70 for each configuration the pwm from the digital driver are mapped in different way to the power stage: 2.0 channels, two full bridges (ocfg = 00) " ddx1a out1a " ddx1b out1b " ddx2a out2a " ddx2b out2b " ddx3a out3a " ddx3b out3b " ddx4a out4a " ddx4b out4b " ddx1a/1b configured as ternary " ddx2a/2b configured as ternary " ddx3a/3b configured as line-out ternary " ddx4a/4b configured as line-out ternary on channel 3 line out (loc bits = 00) the same data as channel 1 processing are sent. on channel 4 line out (loc bits = 00) the same data as channel 2 processing are sent. in this configuration, no volume control or eq have effect on channel 3 and 4. in this configuration the pwm slot phase is the following as shown in the next figures. figure 13. 2.0 channels (ocfg = 00) pwm slots out1a out1b out2a out2b out3a out3b out4a out4b
STA335BWSQS register description 39/70 2.1 channels, two half bridges + one full bridge (ocfg = 01) " ddx1a out1a " ddx2a out1b " ddx3a out2a " ddx3b out2b " ddx1a out3a " ddx1b out3b " ddx2a out4a " ddx2b out4b " ddx1a/1b configured as binary " ddx2a/2b configured as binary " ddx3a/3b configured as binary " ddx4a/4b is not used in this configuration, channel 3 has full control (for example, on volume and eq). on out3/out4 channels the channel 1 and channel 2 pwm are replicated. in this configuration the pwm slot phase is the following as shown in the next figures: figure 14. 2.1 channels (ocfg = 01) pwm slots out1a out2a out2b out3a out3b out1b out4a out4b out1a out2a out2b out3a out3b out1b out4a out4b
register description STA335BWSQS 40/70 2.1 channels, two full bridge + one external full bridge (ocfg = 10) " ddx1a out1a " ddx1b out1b " ddx2a out2a " ddx2b out2b " ddx3a out3a " ddx3b out3b " eapd out4a " twarn out4b " ddx1a/1b configured as ternary " ddx2a/2b configured as ternary " ddx3a/3b configured as ternary " ddx4a/4b is not used in this configuration, channel 3 has full control (volume, eq, etc?). on out4 channel the external bridge control signals are muxed. in this configuration the pwm slot phase is the following as shown in the next figures: figure 15. 2.1 channels (ocfg = 10) pwm slots 6.6.2 invalid input detect mute enable setting the ide bit enables this function, which looks at the input i 2 s data and will automatically mute if the signals are perceived as invalid. out1a out1b out2a out2b out3a out3b out1a out1b out2a out2b out3a out3b table 45. ide bit rw rst name description 2rw 1 ide setting of 1 enables the automatic invalid input detect mute
STA335BWSQS register description 41/70 6.6.3 binary output mode clock loss detection detects loss of input mclk in bina ry mode and will outpu t 50% duty cycle. 6.6.4 lrck double trigger protection actively prevents double trigger of lrclk. 6.6.5 auto eapd on clock loss when active, issues a power device power down signal (eapd) on clock loss detection. 6.6.6 ic power down the pwdn register is used to place the ic in a low-power state. when pwdn is written as 0, the output begins a soft-mute. after the mute condition is reached, eapd is asserted to power down the power-stage, then the master clock to all internal hardware expect the i 2 c block is gated. this places the ic in a very low power consumption state. 6.6.7 external am plifier power down the eapd register directly disables/enables the internal power circuitry. when eapd = 0, the internal power section is placed on a low-power state (disabled). this register also controls the ddx4b/eapd output pin when ocfg = 10. table 46. bcle bit rw rst name description 3 rw 1 bcle binary output mode clock loss detection enable table 47. ldte bit rw rst name description 4 rw 1 ldte lrclk double trigger protection enable table 48. ecle bit rw rst name description 5 rw 0 ecle auto eapd on clock loss table 49. pwdn bit rw rst name description 7rw 1 pwdn 0: ic power down low-power condition 1: ic normal operation table 50. eapd bit rw rst name description 7 rw 0 eapd 0: external power stage power down active 1: normal operation
register description STA335BWSQS 42/70 6.7 volume control regist ers (addr 0x06 to 0x0a) 6.7.1 mute/line output configuration register line output is only active when ocfg = 00. in this case loc determines the line output configuration. the source of the line output is always the channel 1 and 2 inputs. 6.7.2 master volume register 6.7.3 channel 1 volume 6.7.4 channel 2 volume d7 d6 d5 d4 d3 d2 d1 d0 loc1 loc0 reserved c3m c2m c1m mmute 00 0000 table 51. loc loc[1:0] line output configuration 00 line output fixed - no volume, no eq 01 line output variable - ch3 volume effects line output, no eq 10 line output variable with eq - ch3 volume effects line output d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000
STA335BWSQS register description 43/70 6.7.5 channel 3 and line-output volume the volume structure of the STA335BWSQS consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. the individual channel volumes are adjustable in 0.5-db steps from +48 db to -80 db. as an example if c3v = 0x00 or +48 db and mv = 0x18 or -12 db, then the total gain for channel 3 = +36 db. the master mute when set to 1 mutes all channels at once, whereas the individual channel mutes (cxm) mutes only that channel. both the master mute and the channel mutes provide a ?soft? mute with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 khz). a ?hard mute? can be obtained by commanding a value of 0xff (255) to any channel volume register or the master volume register. when volume offsets are provided via the master volume register any channel that whose total volume is less than -80 db is muted. all changes in volume take place at zero-crossings when zce = 1 (configuration register f) on a per channel basis as this creates the smoothest possible volume transitions. when zce = 0, volume updates occur immediately. d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 01100000 table 52. master volume offset as a function of mv[7:0] mv[7:0] volume offset from channel value 00000000 (0x00) 0 db 00000001 (0x01) -0.5 db 00000010 (0x02) -1 db ?? 01001100 (0x4c) -38 db ?? 11111110 (0xfe) -127.5 db 11111111 (0xff) hard master mute table 53. channel volume as a function of cxv[7:0] cxv[7:0] volume 00000000 (0x00) +48 db 00000001 (0x01) +47.5 db 00000010 (0x02) +47 db ?? 01011111 (0x5f) +0.5 db 01100000 (0x60) 0 db 01100001 (0x61) -0.5 db
register description STA335BWSQS 44/70 6.8 automode registers (addr 0x0b and 0x0c) 6.8.1 automode regist er 1 (address 0x0b) amgc[1:0], in conjunction with amgc[3:2] defined in register 0x31, defines anti-clipping and drc presets. using amgc[3:0] bits, atta ck and release thresholds and rates are automatically configured to properly fit application specific configuration. 6.8.2 automode regist er 2 (address 0x0c) ?? 11010111 (0xd7) -59.5 db 11011000 (0xd8) -60 db 11011001 (0xd9) -61 db 11011010 (0xda) -62 db ?? 11101100 (0xec) -80 db 11101101 (0xed) hard channel mute ?? 11111111 (0xff) hard channel mute table 53. channel volume as a function of cxv[7:0] (continued) cxv[7:0] volume d7 d6 d5 d4 d3 d2 d1 d0 reserved amgc1 amgc2 reserved 00 table 54. automode gain compression/limiters selection amgc[1:0] mode 00 user programmable gc 01 ac no clipping 2.1 10 ac limited clipping (10%) 2.1 11 drc nighttime listening mode 2.1 d7 d6 d5 d4 d3 d2 d1 d0 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 00000000
STA335BWSQS register description 45/70 6.8.3 am interference frequency switching 6.8.4 bass management crossover table 55. amame bit rw rst name description 0 rw 0 amame automode am enable 0: switching frequency determined by pwms setting 1: switching frequency determined by amam settings table 56. automode am switching frequency selection amam[2:0] 48 khz/96 khz input fs 44.1 khz/88.2 khz input fs 000 0.535 mhz - 0.720 mhz 0.535 mhz - 0.670 mhz 001 0.721 mhz - 0.900 mhz 0.671 mhz - 0.800 mhz 010 0.901 mhz - 1.100 mhz 0.801 mhz - 1.000 mhz 011 1.101 mhz - 1.300 mhz 1.001 mhz - 1.180 mhz 100 1.301 mhz - 1.480 mhz 1.181 mhz - 1.340 mhz 101 1.481 mhz - 1.600 mhz 1.341 mhz - 1.500 mhz 110 1.601 mhz - 1.700 mhz 1.501 mhz - 1.700 mhz table 57. xo bit rw rst name description 4rw 0 xo0 selects the bass-management crossover frequency. a 1st-order high-pass filter (channels 1 and 2) or a 2nd-order low-pass filter (channel 3) at the selected frequency is performed. 5rw 0 xo1 6rw 0 xo2 7rw 0 xo3 table 58. bass management crossover frequency xo[3:0] crossover frequency 0000 user-defined 0001 80 hz 0010 100 hz 0011 120 hz 0100 140 hz 0101 160 hz 0110 180 hz 0111 200 hz 1000 220 hz 1001 240 hz
register description STA335BWSQS 46/70 6.9 channel configuration re gisters (addr 0x0e to 0x10) 6.9.1 tone control bypass tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2. cxtcb: 0: perform tone control on channel x (normal operation) 1: bypass tone control on channel x 6.9.2 eq bypass eq control can be bypassed on a per channel basis for channels 1 and 2. if eq control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. cxeqbp: 0: perform eq on channel x - normal operation 1: bypass eq on channel x 1010 260 hz 1011 280 hz 1100 300 hz 1101 320 hz 1110 340 hz 1111 360 hz table 58. bass management crossover frequency (continued) xo[3:0] crossover frequency d7 d6 d5 d4 d3 d2 d1 d0 c1om1 c1om0 c1ls1 c1ls0 c1bo c1vpb c1eqbp c1tcb 000000 0 0 d7 d6 d5 d4 d3 d2 d1 d0 c2om1 c2om0 c2ls1 c2ls0 c2bo c2vpb c2eqbp c2tcb 010000 0 0 d7 d6 d5 d4 d3 d2 d1 d0 c3om1 c3om0 c3ls1 c3ls0 c3bo c3vpb reserved 100000
STA335BWSQS register description 47/70 6.9.3 volume bypass each channel contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volu me setting will not affect that channel. 6.9.4 binary output enable registers each individual channel output can be set to output a binary pwm stream. in this mode output a of a channel is considered the positive output and output b is negative inverse. cxbo: 0: ddx 3-state output - normal operation 1: binary output 6.9.5 limiter select limiter selection can be made on a per-channel basis according to the channel limiter select bits. . 6.9.6 output mapping output mapping can be performed on a per channel basis according to the cxom channel output mapping bits. each input into the output configuration engine can receive data from any of the three processing channel outputs. . table 59. channel limiter mapping as a function of cxls bits cxls[1,0] channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 table 60. channel output mapping as a function of cxom bits cxom[1,0] channel x output source from 00 channel1 01 channel 2 10 channel 3
register description STA335BWSQS 48/70 6.10 tone control register (addr 0x11) 6.10.1 tone control 6.11 dynamics control registers (addr 0x12 to 0x15) 6.11.1 limiter 1 attack/release rate 6.11.2 limiter 1 attack/release threshold 6.11.3 limiter 2 attack/release rate d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 table 61. tone control boost/cut as a function of btc and ttc bits btc[3:0]/ttc[3:0] boost/cut 0000 -12 db 0001 -12 db ?? 0111 -4 db 0110 -2 db 0111 0 db 1000 +2 db 1001 +4 db ?? 1101 +12 db 1110 +12 db 1111 +12 db d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101 0 1 0
STA335BWSQS register description 49/70 6.11.4 limiter 2 attack/release threshold the STA335BWSQS includes two independent limiter blocks. the purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for dvds. the two modes are selected via the drc bit in configuration register f, bit 0 address 0x05. each channel can be mapped to either limiter or not mapped, me aning that channel will clip when 0 dbfs is exceeded. each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison. the limiter attack thresholds are determined by the lxat registers. it is recommended in anti-clipping mode to set this to 0 dbfs, which corresponds to the maximum unclipped output power of a ddx ? amplifier. since gain can be added digitally within STA335BWSQS it is possible to exceed 0 dbfs or any other lxat setting, when this occurs, the limiter, when active, automatically starts reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. the gain reduction occurs on a peak-detect algorithm. the release of limiter, when the gain is again increased, is dependent on a rms-detect algorithm. the output of the volume/limiter block is passed through a rms filter. the output of this filter is compared to the release threshold, determined by the release threshold register. when the rms filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. the gain can never be increased past it's set value and therefore the release only occurs if the limiter has already reduced the gain. the release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound ?lifeless?. in ac mode, the attack and re lease thresholds are set relati ve to full-scale. in drc mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is se t relative to the maximum volume setting plus the attack threshold. d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101 0 0 1
register description STA335BWSQS 50/70 figure 16. basic limiter and volume flow diagram table 62. limiter attack rate as a function of lxa bits table 63. limiter release rate as a function of lxr bits lxa[3:0] attack rate db/ms lxr[3:0] release rate db/ms 0000 3.1584 fast slow 0000 0.5116 fast slow 0001 2.7072 0001 0.1370 0010 2.2560 0010 0.0744 0011 1.8048 0011 0.0499 0100 1.3536 0100 0.0360 0101 0.9024 0101 0.0299 0110 0.4512 0110 0.0264 0111 0.2256 0111 0.0208 1000 0.1504 1000 0.0198 1001 0.1123 1001 0.0172 1010 0.0902 1010 0.0147 1011 0.0752 1011 0.0137 1100 0.0645 1100 0.0134 1101 0.0564 1101 0.0117 1110 0.0501 1110 0.0110 1111 0.0451 1111 0.0104
STA335BWSQS register description 51/70 anti-clipping mode table 64. limiter attack threshold as a function of lxat bits (ac-mode) table 65. limiter release threshold as a function of lxrt bits (ac-mode) lxat[3:0] ac (db relative to fs) lxrt[3:0] ac (db relative to fs) 0000 -12 0000 - 0001 -10 0001 -29 db 0010 -8 0010 -20 db 0011 -6 0011 -16 db 0100 -4 0100 -14 db 0101 -2 0101 -12 db 0110 0 0110 -10 db 0111 +2 0111 -8 db 1000 +3 1000 -7 db 1001 +4 1001 -6 db 1010 +5 1010 -5 db 1011 +6 1011 -4 db 1100 +7 1100 -3 db 1101 +8 1101 -2 db 1110 +9 1110 -1 db 1111 +10 1111 -0 db
register description STA335BWSQS 52/70 dynamic range compression mode 6.12 user-defined coefficient contro l registers (addr 0x16 to 0x26) 6.12.1 coefficient address register 6.12.2 coefficient b1 data register bits 23:16 table 66. limiter attack threshold as a function of lxat bits (drc-mode) table 67. limiter release threshold as a as a function of lxrt bits (drc-mode) lxat[3:0] drc (db relative to volume) lxrt[3:0] drc (db relative to volume + lxat) 0000 -31 0000 - 0001 -29 0001 -38 db 0010 -27 0010 -36 db 0011 -25 0011 -33 db 0100 -23 0100 -31 db 0101 -21 0101 -30 db 0110 -19 0110 -28 db 0111 -17 0111 -26 db 1000 -16 1000 -24 db 1001 -15 1001 -22 db 1010 -14 1010 -20 db 1011 -13 1011 -18 db 1100 -12 1100 -15 db 1101 -10 1101 -12 db 1110 -7 1110 -9 db 1111 -4 1111 -6 db d7 d6 d5 d4 d3 d2 d1 d0 reserved cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000
STA335BWSQS register description 53/70 6.12.3 coefficient b1 dat a register bits 15:8 6.12.4 coefficient b1 dat a register bits 7:0 6.12.5 coefficient b2 data register bits 23:16 6.12.6 coefficient b2 dat a register bits 15:8 6.12.7 coefficient b2 dat a register bits 7:0 6.12.8 coefficient a1 data register bits 23:16 6.12.9 coefficient a1 dat a register bits 15:8 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000
register description STA335BWSQS 54/70 6.12.10 coefficient a1 dat a register bits 7:0 6.12.11 coefficient a2 dat a register bits 23:16 6.12.12 coefficient a2 dat a register bits 15:8 6.12.13 coefficient a2 dat a register bits 7:0 6.12.14 coefficient b0 dat a register bits 23:16 6.12.15 coefficient b0 dat a register bits 15:8 6.12.16 coefficient b0 dat a register bits 7:0 d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000
STA335BWSQS register description 55/70 6.12.17 coefficient write /read control register coefficients for user-defined eq, mixing, scaling, and bass management are handled internally in the STA335BWSQS vi a ram. access to this ram is available to the user via an i 2 c register interface. a collection of i2c registers are dedicated to this function. one contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from ram. three different ram banks are embedded in STA335BWSQS. the three banks are managed in paging mode using eqcfg register bits. they can be used to store different eq settings. for speaker frequency compensation, a sampling frequency independent eq must be implemented. computing 3 different coefficients set for 32 khz, 44.1khz, 48 khz and downloading them in the 3 ram banks, it is possible to select the suitable ram block depending from the incoming frequency with a simple i 2 c write operation on register 0x31. for example, in case of different input sources (different sampling rates), the 3 different set of coefficients can be downloaded once at the start up, and during the normal play it is possible to switch among the 3 ram blocks allowing a faster operation, without any additional download from the microcontroller. to write the coefficients in a particular ram bank, this bank must be selected first writing bit 0 and bit 1 in register 0x31. then the below write procedure can be used. note that as soon as a ram bank is selected , the eq settings will be automatically switched to the coefficients stored in the active ram block. note: the read and write operation on ram coefficients works only if lrcki (pin 29) is switching. reading a coefficient from ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of address to i 2 c register 0x16. 3. write 1 to r1 bit in i 2 c address 0x26. 4. read top 8-bits of coefficient in i 2 c address 0x17. 5. read middle 8-bits of coefficient in i 2 c address 0x18. 6. read bottom 8-bits of coefficient in i 2 c address 0x19. reading a set of coefficients from ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of address to i 2 c register 0x16. 3. write 1 to ra bit in i 2 c address 0x26. 4. read top 8-bits of coefficient in i 2 c address 0x17. 5. read middle 8-bits of coefficient in i 2 c address 0x18. 6. read bottom 8-bits of coefficient in i 2 c address 0x19. 7. read top 8-bits of coefficient b2 in i 2 c address 0x1a. 8. read middle 8-bits of coefficient b2 in i 2 c address 0x1b. d7 d6 d5 d4 d3 d2 d1 d0 reserved ra r1 wa w1 0000
register description STA335BWSQS 56/70 9. read bottom 8-bits of coefficient b2 in i 2 c address 0x1c. 10. read top 8-bits of coefficient a1 in i 2 c address 0x1d. 11. read middle 8-bits of coefficient a1 in i 2 c address 0x1e. 12. read bottom 8-bits of coefficient a1 in i 2 c address 0x1f. 13. read top 8-bits of coefficient a2 in i 2 c address 0x20. 14. read middle 8-bits of coefficient a2 in i 2 c address 0x21. 15. read bottom 8-bits of coefficient a2 in i 2 c address 0x22. 16. read top 8-bits of coefficient b0 in i 2 c address 0x23. 17. read middle 8-bits of coefficient b0 in i 2 c address 0x24. 18. read bottom 8-bits of coefficient b0 in i 2 c address 0x25. writing a single coefficient to ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of address to i 2 c register 0x16. 3. write top 8-bits of coefficient in i 2 c address 0x17. 4. write middle 8-bits of coefficient in i 2 c address 0x18. 5. write bottom 8-bits of coefficient in i 2 c address 0x19. 6. write 1 to w1 bit in i 2 c address 0x26. writing a set of coefficients to ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of starting address to i 2 c register 0x16. 3. write top 8-bits of coefficient b1 in i 2 c address 0x17. 4. write middle 8-bits of coefficient b1 in i 2 c address 0x18. 5. write bottom 8-bits of coefficient b1 in i 2 c address 0x19. 6. write top 8-bits of coefficient b2 in i 2 c address 0x1a. 7. write middle 8-bits of coefficient b2 in i 2 c address 0x1b. 8. write bottom 8-bits of coefficient b2 in i 2 c address 0x1c. 9. write top 8-bits of coefficient a1 in i 2 c address 0x1d. 10. write middle 8-bits of coefficient a1 in i 2 c address 0x1e. 11. write bottom 8-bits of coefficient a1 in i 2 c address 0x1f. 12. write top 8-bits of coefficient a2 in i 2 c address 0x20. 13. write middle 8-bits of coefficient a2 in i 2 c address 0x21. 14. write bottom 8-bits of coefficient a2 in i 2 c address 0x22. 15. write top 8-bits of coefficient b0 in i 2 c address 0x23. 16. write middle 8-bits of coefficient b0 in i 2 c address 0x24. 17. write bottom 8-bits of coefficient b0 in i 2 c address 0x25. 18. write 1 to wa bit in i 2 c address 0x26. the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. when using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA335BWSQS register description 57/70 STA335BWSQS generates the ram addresses as offsets from this base value to write the complete set of coefficient data. 6.12.18 user-defined eq the STA335BWSQS provides the ab ility to specify four eq filter s (biquads) per each of the two input channels. the biquads use the following equation: y[n] = 2(b 0 /2)x[n] + 2(b 1 /2)x[n-1] + b 2 x[n-2] - 2(a 1 /2)y[n-1] - a 2 y[n-2] = b 0 x[n] + b 1 x[n-1] + b 2 x[n-2] - a 1 y[n-1] - a 2 y[n-2] where y[n] represents the output and x[n] represents the input. multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7fffff (0.9999998808). coefficients stored in the user-defined coefficient ram are referenced as follows: cxhy0 = b 1 /2 cxhy1 = b 2 cxhy2 = -a 1 /2 cxhy3 = -a 2 cxhy4 = b 0 /2 where x represents the channel and the y the biquad number. for example c2h41 is the b 2 coefficient in the fourth biquad for channel 2. additionally, the STA335BWSQS allows specification of a high-pass filter (processing channels 1 and 2) and a lo-pass filter (processing channel 3) to be used for bass-management crossover when the xo setting is 000 (user-defined). both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation noted above. they are loaded into the c12h0-4 and c3hy0-4 areas of ram noted in ta b l e 6 8 . by default, all user-defined filters are pass-through where all coefficients are set to 0, except the b 0 /2 coefficient which is set to 0x400000 (representing 0.5) 6.12.19 pre-scale the STA335BWSQS provides a multiplication for each input channel for the purpose of scaling the input prior to eq. th is pre-eq scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiply is loaded into ram using the same i 2 c registers as the biquad coefficients and the bass-management. all channels can use the channel 1 pre-scale factor by setting the biquad link bit. by default, all pre-scale factors are set to 0x7fffff. 6.12.20 post-scale the STA335BWSQS provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. this post-scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiply is loaded into ram using the same i 2 c registers as the biquad coefficients and the bass-management. this post-scale factor can be used in conjunction with an adc equipped micro-controller to perform power-supply error correction. all channels can use the channel 1 post-scale factor by setting the post-scale link bit. by default, all post-scale factors are set to 0x7fffff. when line output is being used, channel 3 post-scale affects both channels 3 and 4.
register description STA335BWSQS 58/70 6.12.21 over-current post-scale the STA335BWSQS provides a simple mechanism for reacting to over-current detection in the power-block. when the ocwarn input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. the default setting provides 3 db of output attenuation when ocwarn is asserted. the amount of attenuation to be applied in this situation can be adjusted by modifying the over-current post-scale value. as with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. by default, the over-current post-scale factor is set to 0x5a9df7 . once the over-current attenuation is applied, it remains unt il the device is reset. table 68. ram block for biquads, mixing, scaling and bass management index (decimal) index (hex) ram block setting coefficient default 0 0x00 channel 1, biquad 1 c1h10(b1/2) 0x000000 1 0x01 c1h11(b2) 0x000000 2 0x02 c1h12(a1/2) 0x000000 3 0x03 c1h13(a2) 0x000000 4 0x04 c1h14(b0/2) 0x400000 5 0x05 channel 1, biquad 2 c1h20 0x000000 ?? ? ? ? 19 0x13 channel 1, biquad 4 c1h44 0x400000 20 0x14 channel 2, biquad 1 c2h10 0x000000 21 0x15 c2h11 0x000000 ?? ? ? ? 39 0x27 channel 2, biquad 4 c2h44 0x400000 40 0x28 channel 1/2 - biquad 5 for xo = 000 hi-pass 2 nd order filter for xo 000 c12h0(b1/2) 0x000000 41 0x29 c12h1(b2) 0x000000 42 0x2a c12h2(a1/2) 0x000000 43 0x2b c12h3(a2) 0x000000 44 0x2c c12h4(b0/2) 0x400000 45 0x2d channel 3 - biquad for xo = 000 low-pass 2 nd order filter for xo 000 c3h0(b1/2) 0x000000 46 0x2e c3h1(b2) 0x000000 47 0x2f c3h2(a1/2) 0x000000 48 0x30 c3h3(a2) 0x000000 49 0x31 c3h4(b0/2) 0x400000 50 0x32 channel 1, pre-scale c1pres 0x7fffff 51 0x33 channel 2, pre-scale c2pres 0x7fffff 52 0x34 channel 1, post-scale c1psts 0x7fffff 53 0x35 channel 2, post-scale c2psts 0x7fffff
STA335BWSQS register description 59/70 6.13 variable max power correction registers (addr 0x27 to 0x28) mpcc bits determine the 16 msbs of the mpc comp ensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 6.14 variable distortion compen sation registers (addr 0x29 to 0x2a) dcc bits determine the 16 msbs of the distor tion compensation coefficient. this coefficient is used in place of the default coefficient when dccv = 1. 54 0x36 channel 3, post-scale c3psts 0x7fffff 55 0x37 twarn/oc - limit twocl 0x5a9df7 56 0x38 channel 1, mix 1 c1mx1 0x7fffff 57 0x39 channel 1, mix 2 c1mx2 0x000000 58 0x3a channel 2, mix 1 c2mx1 0x000000 59 0x3b channel 2, mix 2 c2mx2 0x7fffff 60 0x3c channel 3, mix 1 c3mx1 0x400000 61 0x3d channel 3, mix 2 c3mx2 0x400000 62 0x3e unused 63 0x3f unused table 68. ram block for biquads, mixing, scaling and bass management index (decimal) index (hex) ram block setting coefficient default d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00011010 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011
register description STA335BWSQS 60/70 6.15 fault detect recovery consta nt registers (addr 0x2b to 0x2c) fdrc bits specify the 16-bit faul t detect recovery time delay. when fault is asserted, the tristate output is immediately asserted low and held low for the time period specified by this constant. a constant value of 0x0001 in this register is approximately 0.083 ms. the default value of 0x000c specifies approximately 0.1 ms. 6.16 device status register (addr 0x2d) this read-only register provides fault and thermal-warning status information from the power control block. logic value 1 for faults or warning means normal state. logic 0 means a fault or warning detected on power bridge. the pllul = 1 means that the pll is not locked. " pllul: 0 = pll locked, 1 = pll not locked. " fault: 0 = fault detected on power bridge, 1 = normal operation " uvfault: 0 = vccx internally detected < undervoltage threshold. " ovfault: 0 = vccx internally detected > overvoltage threshold. " ocfault: 0 = overcurrent fault detected " ocwarn: 0 = overcurrent warning. " tfault: 0 = thermal fault. junction temperature over limit detection. " twarn: 0 = thermal warning. the junction temperature is close to the fault condition. d7 d6 d5 d4 d3 d2 d1 d0 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100 d7 d6 d5 d4 d3 d2 d1 d0 pllul fault uvfault ovfault ocfault ocwarn tfault twarn
STA335BWSQS register description 61/70 6.17 eq coefficients and drc conf iguration register (addr 0x31) ac0, ac1, ac2 settings are designed for loudspeaker protection function, limiting at the minimum any audio artefact introduced by typical anti-clipping/drc algorithms. more detailed information can be retrieved in the ?configurable output power rate using ?sta335bw? and ?sta335bws vs sta335bw? application notes. bit xob can be used to bypass the crossover filters. logic 1 means that the function is not active. in this case, high pass crossover filter works as a pass through on the data path (b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have zero signal on channel 3 data processing (all the coefficients are at logic 0). d7 d6 d5 d4 d3 d2 d1 d0 xob reserved amgc[3] amgc[2] reserved sel1 sel0 00000000 table 69. sel bitfield description sel[1,0] eq ram bank selected 00/11 bank 0 activated 01 bank 1 activated 10 bank 2 activated table 70. amgc bitfield description amgc[3,2] anti-clipping and drc preset selected 00 drc/anti-clipping (default) 01 drc/anti-clipping 10/11 reserved, do not use table 71. amgc bitfield description amgc[1:0] mode 00 ac0, stereo anti-clipping 0db limiter 01 ac1, stereo anti-clipping +1.25db limiter 10 ac2, stereo anti-clipping +2db limiter 11 reserved do not use
applications STA335BWSQS 62/70 7 applications 7.1 applications schema tic and power supplies figure 17 below shows a circuit diagram of a typical application for STA335BWSQS. particular care has to be given to the layout of the pcb, especially the power supplies. the 3.3- ? resistors on the digital supplies (vdd_dig) have to be placed as close as possible to the device. this helps to prevent unwanted oscilla tion on the digital portion of the device due to inductive tracks of the pcb. this same rule also applies to all the decoupling capacitors in order to limit any kind of spikes on the supplies. figure 17. application schematic 7.2 pll filter schematic it is recommended to use the schematic and values in figure 18 below for the pll loop filter. in order to achieve the best performance from the device in general applications the filter ground (pll_gnd) must be connected as close as possible to the device pin pll_gnd. concerning the component values, please take into account that the greater is the filter bandwidth, the less is the lock time but the higher is the pll output jitter. figure 18. pll application scheme 100nf + 1000uf 35v 1nf scl sda reset vcc reset 100nf tw eapd 3v3 1uf 35v 100nf 100nf 1uf 35v intl 100nf 100nf 3v3 3v3 3r3 ddx3b ddx3a 3r3 lrcki pwdn 3v3 out2b xti bicki out2a gnd_sub 1 sa 2 test_mode 3 vss 4 vcc_reg 5 out2b 6 gnd2 7 vcc2 8 out2a 9 out1b 10 vcc1 11 gnd1 12 out1a 13 gnd_reg 14 vdd 15 config 16 ddx3b 17 ddx3a 18 eapd/4b 19 twarn/4a 20 vdd_dig 21 gnd_dig 22 pwrdn 23 vdd_pll 24 filter_pll 25 pll_gnd 26 xti 27 bicki 28 lrcki 29 sdi 30 reset 31 int_line 32 sda 33 scl 34 gnd_dig 35 vdd_dig 36 out1b data pll_filt out1a 10k 100nf + 1000uf 35v 1nf scl sda reset vcc reset 100nf 100nf out2a gnd_sub 1 sa 2 test_mode 3 vss 4 vcc_reg 5 out2b 6 gnd2 7 vcc2 8 out2a 9 out1b 10 vcc1 11 gnd1 12 out1a 13 gnd_reg 14 vdd 15 config 16 ddx3b 17 ddx3a 18 eapd/4b 19 twarn/4a 20 vdd_dig 21 gnd_dig 22 pwrdn 23 vdd_pll 24 filter_pll 25 pll_gnd 26 xti 27 bicki 28 lrcki 29 sdi 30 reset 31 int_line 32 sda 33 scl 34 gnd_dig 35 vdd_dig 36 out1b data pll_filt out1a 10k bead bead pll_gnd gnd_dig gnd_dig gnd_dig gnd_dig 100nf + 1000uf 35v 1nf scl sda reset vcc reset 100nf tw eapd 3v3 1uf 35v 100nf 100nf 1uf 35v intl 100nf 100nf 3v3 3v3 3r3 ddx3b ddx3a 3r3 lrcki pwdn 3v3 out2b xti bicki out2a gnd_sub 1 sa 2 test_mode 3 vss 4 vcc_reg 5 out2b 6 gnd2 7 vcc2 8 out2a 9 out1b 10 vcc1 11 gnd1 12 out1a 13 gnd_reg 14 vdd 15 config 16 ddx3b 17 ddx3a 18 eapd/4b 19 twarn/4a 20 vdd_dig 21 gnd_dig 22 pwrdn 23 vdd_pll 24 filter_pll 25 pll_gnd 26 xti 27 bicki 28 lrcki 29 sdi 30 reset 31 int_line 32 sda 33 scl 34 gnd_dig 35 vdd_dig 36 out1b data pll_filt out1a 10k 100nf + 1000uf 35v 1nf scl sda reset vcc reset 100nf 100nf out2a gnd_sub 1 sa 2 test_mode 3 vss 4 vcc_reg 5 out2b 6 gnd2 7 vcc2 8 out2a 9 out1b 10 vcc1 11 gnd1 12 out1a 13 gnd_reg 14 vdd 15 config 16 ddx3b 17 ddx3a 18 eapd/4b 19 twarn/4a 20 vdd_dig 21 gnd_dig 22 pwrdn 23 vdd_pll 24 filter_pll 25 pll_gnd 26 xti 27 bicki 28 lrcki 29 sdi 30 reset 31 int_line 32 sda 33 scl 34 gnd_dig 35 vdd_dig 36 out1b data pll_filt out1a 10k bead bead bead pll_gnd gnd_dig gnd_dig gnd_dig gnd_dig 100pf filter_pll 680pf 4.7nf 2k2 100pf filter_pll 680pf 4.7nf 2k2 bead pll_gnd gnd_dig 100pf filter_pll 680pf 4.7nf 2k2 100pf filter_pll 680pf 4.7nf 2k2 bead bead pll_gnd gnd_dig component leads must be kept as short as possible
STA335BWSQS applications 63/70 7.3 typical output configuration figure 19 shows the typical output configuration used for btl stereo mode. please refer to the application note for other recommended output configuration schematics. figure 19. output configuration for stereo btl mode 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2
package thermal characteristics STA335BWSQS 64/70 8 package thermal characteristics using a double-layer pcb the thermal resistance (junction to ambient) with two copper ground areas of 3 x 3 cm 2 and with 16 via holes (see figure 20 ) is 24 c/w in natural air convection. the dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. the estimated maximum dissipated power for the STA335BWSQS is: figure 20. double-layer pcb with copper ground area and 16 via holes figure 21 shows the power derating curves for the powersso-36 package on a board with two different sizes of copper layers. figure 21. powersso-36 power derating curves 8.1 thermal data 2 x 20 w into 8 ? at 18 v pd max ~ 4 w 2 x 10 w + 1 x 20 w into 4 ? , 8 ? at 18 v pd max < 5 w 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta335bw psso36 copper area 3x3 cm and via holes STA335BWSQS powersso-36 table 72. thermal data parameter min typ max unit r th j-case thermal resistance junction-case (thermal pad) 1.5 c/w t th-sdj thermal shut-down junction temperature 150 c
STA335BWSQS package thermal characteristics 65/70 t th-w thermal warning temperature 130 c t th-sdh thermal shut-down hysteresis 20 c r th j-amb thermal resistance junction-ambient table 72. thermal data (continued) parameter min typ max unit
package information STA335BWSQS 66/70 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. figure 22. powersso-36 (slug-up) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.15 2.47 0.084 0.097 a2 2.15 2.40 0.084 0.094 a1 0 0.075 0 0.003 b 0.18 0.36 0.007 0.014 c 0.23 0.32 0.009 0.012 d (1) 10.10 10.50 0.398 0.413 e (1) 7.4 7.6 0.291 0.299 e 0.5 0.019 e3 8.5 0.335 f 2.3 0.090 g 0.10 0.004 g1 0.06 0.002 h 10.10 10.50 0.398 0.413 h 0.40 0.016 k5? 5? l 0.55 0.90 0.022 0.035 m 4.3 0.169 n 10? 10? o 1.2 0.047 q 0.8 0.031 s 2.9 0.114 t3.65 0.144 u 1.0 0.039 x 4.1 4.7 0.161 0.185 y 6.5 7.3 0.256 0.287 (1) "d? and ?e" do not include mold flash or protrusions mold flash or protrusions shall not exceed 0.15 mm per side(0.006?) powersso-36 7587131 a (slug-down) g lead coplanarity bottom view e h d e3 f 0.1 a m b b e a y stand-off x c t m q s l gauge plane 0.25 k a a2 hx45? a1 u o b
STA335BWSQS license information 67/70 10 license information supply of this product does not convey a license under the relevant intellectual property of the companies mentioned in this chapter nor imply any right to use this intellectual property in any finished end-user or ready to use final product. an independent license for such use is required and can be obtained by contacting the company or companies concerned. once the license is obtained, a copy must be sent to stmicroelectronics. the details of all the features requiring licenses are not provided within the datasheet and register manual. they are provided only after a copy of the license has been received by stmicroelectronics. the feature requiring license is: qxpander ? , qhd ? qhd ? and qxpander ? are intellectual property of qsound labs inc. a license can be obtained with the STA335BWSQS via stmicroelectronics,please contact the hpc audio division product manager for details. alternatively the license can be obtained directly from qsound labs inc. for details please contact: sales@qsound.com or qsound labs, inc 400 - 3115 12th street ne calgary, ab canada t2e 7j2
trademarks and other acknowledgements STA335BWSQS 68/70 11 trademarks and other acknowledgements ddx is a registered trademark of apogee technology inc. sound terminal is a trademark of stmicroelectronics. ecopack is a registered trademark of stmicroelectronics. qhd and qxpander are registered trademarks of qsound labs inc.
STA335BWSQS revision history 69/70 12 revision history table 73. document revision history date revision changes 05-mar-2009 1 initial release.
STA335BWSQS 70/70 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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